Field of the Invention
The present invention relates to integrated circuit memory devices, and to circuitry using error correcting codes ECCs.
Description of Related Art
High density memory devices are being designed that include arrays of flash memory cells, or other types of memory cells. In one example, a memory device includes a memory array storing data pages and error correcting codes ECCs for corresponding data pages. The device includes ECC logic to detect and correct errors in the corresponding data pages using the ECCs. The device includes a page buffer coupled to the memory array, to the ECC logic, and to a data path. The page buffer includes sense amplifiers for read operations, a program buffer for write operations, and a cache for read and write operations on data in a data page.
For read operations, data from a data page and error correcting codes ECCs for the page are moved from the memory array to the sense amplifiers, and then from the sense amplifiers to the cache. If the ECC logic is enabled, the ECC logic is then applied on the data using corresponding ECCs, and corrected data is stored in the cache. Corrected data is then moved from the cache to the data path. However, data from a next data page cannot be moved to the cache until after the corrected data in the cache has been moved from the cache to the data path. This results in a lower read throughput for the memory device.
It is desirable to improve the read throughput of a memory device that uses built-in error correcting codes ECCs.